Flesher TU-300 Notes

The Flesher TU-300 and TU-170A are largely the same unit. The TU-170A has fewer filter boards since it only does 170 Hz shift.

As I do work on these units, I will document what I find here.

Resources

Manuals and schematics are located here. Documentation on this product is somewhat limited and unclear.

AFSK Generator

I had to repair the AFSK generator. Here are some notes.

The schematic of the AFSK generator board is here. This board takes a different approach than the AFSK generator in the TU-170, which uses a 555 - based RC oscillator. The TU-300 uses a crystal oscillator with a variable integer divider. IC1 is a crystal oscillator operating at 5.5085 MHz. In the unit I was working on, there is a trace from pin 13 to the crystal that passes between pins 2 and 3 on the top of the board. I found IC1-13 stuck high due to a short between the trace and pins 2 and 3 on the top of the board. Clearing this short allowed the oscillator to run.

The variable integer divider is based on the CD40193 presettable up/down counter. As shown in figure 18, two counters are cascaded to form an 8 bit counter. The clock up pin (5) is tied high, and the crystal oscillator drives the clock down input. On each positive edge of the oscillator output, the 8 bit counter counts down. When the counter decrements from 0 to 0xff, the BORROWn output of IC3 (pin 13) goes low, driving the PRESETn inputs of IC2 and IC3 (pin 11) low, reloading the counter (8 bit due cascaded IC2 and IC3) with the value on the J inputs. The J inputs are pulled high by a SIP resistor network and pulled low by diodes on the AFSK generator board or one of the filter boards. The diodes on the AFSK generator board pull the J inputs of the counter low when FREQSELn is pulled low, indicating we want to output the CW ID frequency. The diodes on the AFSK generator board determine the CW ID frequency. The mark and various space frequencies are determined by the diodes on the corresponding filter board. The divider ratio is the binary code on the J inputs PLUS ONE. If, for example, the J input was 1 (0b00000001), the counter would decrement to zero on the first positive edge of the clock, then decrement to 0xff on the second positive clock edge, generating a BORROWn pulse which reloads the counter. With the J input set to 1, there is a BORROWn pulse for every two incoming clocks. The divide ratio is the J input + 1.

When the TU was transmitting a mark tone (2.125 kHz), the following logic levels were measured:

• IC3-9 - 1
• IC3-10 - 0
• IC3-1 - 1
• IC3-15 - 0
• IC2-9 - 0
• IC2-10 - 0
• IC2-1 - 0
• IC2-15 - 1

On one unit, we found that IC4 was false clocking on the short 34 kHz pulses from IC3 resulting in a higher frequency coming out of IC4 than going in (the output should be the input divided by 16). The output of IC3 (the 72 ns pulse at 34 kHz) looked pretty clean. The false clocking could be seen on the QA output of IC4. That output should be 17 kHz, but was substantially higher. Putting a scope on IC4-3 (clock input) made the false clocking stop. I added a 100 pF capacitor between IC4-3 (clock input) and IC4-5 (+12V). This stopped the false clocking and resulted in the correct frequency out of IC4 (2.125 kHz).

Waveforms

The image at the right is the output of the crystal oscillator (U2-4). Note the frequency is 5.5 MHz.
The image at the right is the BORROWn output of the first divider (IC2-13). Note the frequency is 344 kHz. There is a bit of a shadow on the trace due to false triggering of the scope.
The image at the right is the output of the second divider (IC3-13). Note the frequency is 34 kHz. These pulses are quite narrow since they drive the PRESETn input to the counter which immediately changes the counter value away from 0xff to the preset value.
The image at the right is a closer look at the output of the second divider (IC3-13). This narrow (72 ns) pulse is generated when the 8 bit counter decrements from 0x0 to 0xff, generating a BORROWn output. The BORROWn output loads the counter with the 8 bit binary code on the J inputs to the counters. Once this code is loaded, the BORROWn output goes high, resulting in a short duration pulse on BORROWn. The final divide by 16 chip (IC4) counts these pulses to divide by 16 resulting in the final AFSK audio frequency.
The image at the right is the output of the divide by 16 counter (IC4-7). This is the 2.125 kHz mark signal.

Rear Panel Connections

The manual does not include a table describing the signals on the rear panel connectors. The tables below are derived from the schematics.

P1 Pin Out

P2 Pin Out

Loop Driver

The design of a loop driver that interfaces a 60 mA loop to the TTL interface on P2 is here.

Filter Board